Technology Mapping for FPGAs

1. Robert L. Ashenhurst. "The Decomposition of Switching Functions" Intl. Symposium on the Theory of Swithching. 1957 Harvard University.

2. Roth J.P., and Karp R.M.: "Minimization over Boolean Graphs", IBM Journal of Research and Development, vol. 6, no. 2, pp. 227-238, April 1962.

3. Bryant, Randal E. "Graph-Based Algorithms for Boolean Function Manipulation" IEEE Transactions on Computers August 1986

4. Stanion, Ted and Sechen, Carl: "A method for finding good Ashenhurst decompositions and its application to FPGA synthesis" 32nd DAC 1995

5. E.L. Lawler, K.N. Levitt, J. Turner. "Module clustering to minimize delay in digital networks", IEEE Trans. Comput. 18 (1) (1969) 47-57.

6. J. Cong, Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Trans. on CAD, pp. 1-12, Jan. 1994.

Routability and Technology Mapping for FPGAs

1. El Gamal, A.: Two-dimensional stochastic model for interconnections in master slice cirucits," IEEE Transaction on Circuits and Systems, pp. 127-138, February 1981.

2. P. K. Chan, M. D. F. Schlag, and J. Y. Zien, "On routability prediction for field-programmable gate arrays," in Proc. DAC, Dallas, TX, 1993, pp. 326--330.

3. Martine Schlag, Jackson Kong, and Pak K. Chan, Routability-Driven Technology Mapping for Lookup Table-Based FPGA's, IEEE Trans. on Computer-Aided Design, 13 13--26, 1994

Placement

1. Chih-Liang Eric Cheng, RISA: accurate and efficient placement routability modeling Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design. San Jose, California, United States Pages: 690 - 695 1994

2. Betz, Vaughn and Rose, Jonathan, "VPR: A New Packing, Placement and Routing Tool for FPGA Research". International Workshop on Field Programmable Logic and Applications. 1997

3. A. Marquardt, V. Betz and J. Rose, ``Timing-Driven Placement for FPGAs,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2000, pp. 203 - 213.

4. Hutton, Michael, Adibsamii, Khosrow and Leaver, Andrew, "Timing-driven placement for hierarchical programmable logic devices" Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate array February 2001

5. Eisenmann, Hans, Johannes, Frank M., "Generic global placement and floorplanning", Proceedings of the 35th annual conference on Design Automation San Francisco, California,

6. Shahookar, K., Mazumder, P., VLSI cell placement techniques ACM Computing Surveys (CSUR), Volume 23 Issue 2 June 1991

7. Shewchuk, Jonathan Richard, "An Introduction to the Conjugate Gradient Method Without the Agonizing Pain", (Edition 1 1/4) August 4, 1994

Routing

1. Larry McMurchie , Carl Ebeling, "PathFinder: a negotiation-based performance-driven ro uter for FPGAs", Proceedings of the 1995 ACM third international symposium on FPGAs, p.111-117, February 12-14, 1995, Monterey, California, United States

Retiming

1. Peichen Pan, C. L. Liu, "Optimal clock period FPGA technology mapping for sequential circuits." ACM Transactions on Design Automation of Electronic Systems (TODAES) archive Volume 3 , Issue 3 (July 1998) Pages: 437 - 462

2. Leiserson, Charles E., Saxe, James B., "Retiming synchronous circuitry." SRC-RR-13 August 20, 1986 External

Optimal Technology Mapping

1. Cong, J. and Minkovich, K. "Optimality study of logic synthesis for LUT-based FPGAs" Proceedings of the 2006 ACM/SIGDA 14th international Symposium on Field Programmable Gate Arrays (Monterey, California, USA, February 22 - 24, 2006). FPGA '06. ACM, New York, NY, 33-44.

2. Ling, A., Singh, D. P., and Brown, S. D. "FPGA technology mapping: a study of optimality." In Proceedings of the 42nd Annual Conference on Design Automation (Anaheim, California, USA, June 13 - 17, 2005). DAC '05. ACM, New York, NY, 427-432.

3. Cong, J. and Minkovich, K. "Improved SAT-based Boolean matching using implicants for LUT-based FPGAs." In Proceedings of the 2007 ACM/SIGDA 15th international Symposium on Field Programmable Gate Arrays (Monterey, California, USA, February 18 - 20, 2007). FPGA '07. ACM, New York, NY, 139-147.

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