Optimal Timing Driven Placement

1. Optimality and Stability Study of Timing-Driven Placement Algorithms"
   Jason Cong, Michail Romesis, Min Xie
   Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design November 2003
2. "A novel net weighting algorithm for timing-driven placement"
   Tim (Tianming) Kong
   Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design November 2002

More Technology Mapping

1. "RASP: a general logic synthesis system for SRAM-based FPGAs"
   Jason Cong, John Peck, Yuzheng Ding
   Proceedings of the 1996 ACM fourth international symposium on FPGAs February 1996
2. "Simultaneous depth and area minimization in LUT-based FPGA mapping",
   Jason Cong , Yean-Yow Hwang,
   Proceedings of the 1995 ACM third international symposium on FPGAs p.68-74, February 12-14, 1995, Monterey, California, United States
3. "Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design",
   Jason Cong , Yean-Yow Hwang,
   Proceedings of the 33rd annual conference on Design automation conference, p.726-729, June 03-07, 1996, Las Vegas, Nevada, United States

SAT based routing

1. "FPGA routing and routability estimation via Boolean satisfiability",
   R. Glenn Wood , Rob A. Rutenbar,
   IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.2, p.222-231, June 1998
2. "Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT",
   Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
   Proceedings of the 1999 ACM/SIGDA seventh international symposium on FPGAs
   February 1999

Universal switch modules

1. "On optimum switch box designs for 2-D FPGAs",
   Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung
   Proceedings of the 38th conference on Design automation June 2001
2. "Universal switch modules for FPGA design",
   Yao-Wen Chang , D. F. Wong , C. K. Wong,
   ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.80-101, Jan. 1996

Parallel Placement and Routing for FPGAs

1. "New parallelization and convergence results for NC: a negotiation-based FPGA router"
   Pak K. Chan, Martine D. F. Schlag
   Proceedings of the 2000 ACM/SIGDA eighth international symposium on FPGAs February 2000
2. "Parallel placement for field-programmable gate arrays"
   Pak K. Chan, Martine D. F. Schlag
   Proceedings of the 2003 ACM/SIGDA eleventh international symposium on FPGAs February 2003

Iterative Placement Improvement

1. Compression-relaxation: A New Approach To Performance Driven Placement For Regular Architectures
   Mathur, A.; Liu, C.L.
   Computer-Aided Design, 1994., IEEE/ACM International Conference on Volume , Issue , 6-10 Nov 1994 Page(s):130 - 136

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