CMPE 221 - Advanced Microprocessor Design - Spring 2006
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Paper Reviews

Paper reviews are done individually. Every class, two papers must be reviewed. Paper review must be restricted to 1 page.

Paper reviews during the first week of class will not be graded. The review process will be explained in class. The general principle is the following:

The review must include the following sections: (1 pages total, additional pages will be ignored)

  • Paper title and your name
  • Provide a short summary of the paper
  • What is the strenght? (important)
  • What is the weakness? (important)
  • Provide comments in ways that the paper can be improved
  • Talk about related work published more recently (1-2 paragraphs only)

During class, we will discuss the paper. Students will grade other students papers following some grading suggestions that I will say during the discussion.

Paper Grading

There are a total of 31 papers to read for this class. Each student will choose 25 grades for his grade.

Each week 3 or 4 papers should be reviewed. The reviews should be given to the instructor at the end of the class.

All papers will have a grade between 0 and 10. They will be graded with two different systems:

  • Self-graded: Papers are discussed in class. The instructor will say the main weak/strong points on the paper during class. If the paper has all the main weak/strong papers, it has a perfect grade.
  • Student-graded: Students interchange papers. Other students will grade the paper at home. The reviewed papers are returned to the instructor the next day, and the instructor reviews the grade and the gradding policy.

Reading List

Every class day, you have 2 papers to read. This is a total of 4 papers per week. This will require a substantial amount of effort, this is why paper review represent 40% of the grade.

1st week: Review

  • Complexity-Effective Superscalar Processors (01comeff)

2nd week: Fetch Engine

  • Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching (02trace)
  • Analysis of the O-GEometric History Length Branch Predictor(03trace)
  • An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work (04bpred)
  • Impact of Delay on the Design of Branch Predictors (05bpred)

3rd week: Execute Engine

  • Implementation of Precise Interrupts in Pipelined Processors (06spec)
  • Select-Free Instruction Scheduling Logic (07spec)
  • RENO - A Rename-based Instruction Optimizer (08rat)
  • Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors (09rat)

4th week: Memory Subsystem

  • Virtual Memory in Contemporary Microprocessors (10mem)
  • L1 Cache Decomposition for Energy Efficient Processors (11mem)

5th week: SCOORE, Real Processors

  • Scalable Hardware Memory Disambiguation for High ILP Processors (12ldst)
  • Memory Dependence Predictor using Store Sets (13ldst)
  • Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification (13L0)
  • Power4 System Microarchitecture (14proc)
  • SEED: Scalable, Efficient Enforcement of Dependences

6th week: SMT and Clustered Processors

  • Simultaneous Multithreading: Maximizing On-Chip Parallelism (16smt)
  • Instruction Distribution Heuristics for Quad-Cluster (17cluster)
  • Value Locality and Load Value Prediction (18vpred)
  • Memory Ordering: A Value-Based Approach(19vpred)

7th week: Speculation

  • In Search of Speculative Thread-Level Parallelism (20tls)
  • Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors (21tls)
  • Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors (22ckp)
  • Bulk Disambiguation of Speculative Threads in Multiprocessors (23ckp)

8th week: Energy

  • New methodology for early-stage, microarchitecture-level power performance analysis of microprocessors (24pwr)
  • Temperature-Aware Microarchitecture (25pwr)
  • A Framework for Dynamic Energy Efficiency and Temperature Management(26pwr)
  • Thread-Level Speculation on a CMP Can Be Energy Efficient (27pwr)

9th week: Multiprocessor/Fault-Tolerance

  • Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes(28multi)
  • Performance Evaluation of Memory Consistency Models for Shared-Memory Multiprocessors (29multi)
  • ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors (30ft)
  • Detailed Design and Evaluation of Redundant Multithreading Alternatives (31ft)

Optional Papers

  • Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors (32rat)
  • Circuit Implementation of a 600MHz Superscalar RISC Microprocessor (15proc)
  • Energy-Efficient Thread-Level Speculation on a CMP (21btls)