General Class Information
- Lecture times: Tuesday and Thursday, 2:00-3:45pm
- Class: Kresge Clrm 319
- Instructor: Jose Renau
Office Hours: Friday, 4:00-6:00 PM
Office: E2 227
- Lab time: Friday, 1:00-3:00pm (E2 201)
- Text book: None. See reading list
- Mailing list: SCOORE Mailing list
Grading
- Paper Reviews: 40%
- Project: 60%
Policy
- No exams, midterms, or homeworks. Grading is based on paper reviews
and project.
Class Description
CMPE221 is an introduction to the latest advances in computer
architecture. Focuses on processor core design. Topics include simultaneous
multithreading, thread level speculation, trace caches, novel out-of-order
mechanisms, and energy-efficient processor core designs.
Final project requires the modification/enhancement of a synthesizable
out-of-order processor (FPGA and ASIC target). The class project will
resemble real industry projects. Students will work/collaborate on the
same svn source project. Each group will be in charge of different
processor parts.
Examples of projects: fetch engine, functional units, decode stage,
memory...
Requirements: To take this class you are required to be knowledgeable of
on computer architecture (cmpe202 or equivalent), and to have some
experience with Verilog and/or VHDL (cmpe125/cmpe126 or
equivalent). Concurrent enrollment in the Lab class is required. No
textbook is required.
CMPE221/L (3 credit) consists of weekly two-hour lab session, and 10-15
hours of independent work.
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