Homeworks (individually)
Homeworks should given before 06:00PM of the assigned day. Drop a
printed version at my office. If I am not there, place it under
the door.
Paper Review (individually)
Drop it in my office before 06:00PM of the assigned day.
Choose two papers from paper list
(processor papers are not valid for review). You can choose another paper as
long as it has been
published on MICRO, ISCA, or ASPLOS.
The review must include the following sections: (1-2 pages total)
- Paper title and your name
- Provide a short summary of the paper
- What is the strenght? (important)
- What is the weakness? (important)
- Provide comments in ways that the paper can be improved
- Talk about related work published more recently (1-2
paragraphs only)
- If you choose anothe paper that it is not in the list, add a
printed version of the paper
Setup (individually)
Compile SESC, create a resonable configuration file for a SINGLE
processor, and run 4 SPECints, 2 SPECfps, and 2 splash
benchmarks.
Get SESC from sourceforge. The
precompiled benchmarks with the corresponding input sets can be found on
/projects/masc/software/benchmarks or downloaded (benchmarks.tar.bz2) (100MB
compressed). Note that these files have copyright and they can not be
used/distributed outside of class work. If you need to compile a new
application, you can get the new sescutils
infraestructure.
- I want everybody to keep using the cvs server. At the end of
the project, code modifications should be consistent with the
latest mainline version. Otherwise, the project will not be
accepted.
The report should include (1 page + dump configuration + output report.pl):
- A justification of the parameters choosen. Group justifications, and
try to be short
- A justification for the benchmarks choosen and the input set selected
- The output of report.pl
Projects (individually/group)
Projects should be done either individualy or in groups of two. I will
accept bigger groups only if the tasks are very clearly divided (talk
to me).
Projects have four major parts:
- Project description: A one page document explaining the main objective of the
paper. It should included a clear roadmap. The roadmap includes tasks and who does them.
- Project presentation: 3-4 minutes powerpoint/keynote/latex presentation per each
group member (around 5 slides).
- Project Documentation: A 4-6 pages two column 11pt font size single space. LaTeX
should have a baselinestretch of 1 and article format. The document should have an
introduction, related work, experimental setup, evaluation, and conclusions.
- Project Source: Handle a tar with all the code modifications. The source tree must
be consistent with the latest mainline version. Otherwise, the project will not be
accepted. Remember to read docs/README.codingStyle.
- Project Form must be filled by
each student, and returned before the project due.
List of possible projects (open to other proposals):
- (taken)Compare SESC with 2 other simulators (SESC vs simplescalar vs
RSIM).
- (taken)Compare SESC performance accuracy with native machines (R10K, G4, G5).
- (taken)Transform at least two SPECint benchmarks to GMP library. Compare the performance
impact.
- (taken)Boot sparc-linux on qemu (binary emulator). This requires to implement
several devices like the memory controller on software (qemu).
- (taken)Study branch predictor alternatives for SCOORE (Santa Cruz
Out-of-order Risk Engine) using SESC. Impact on prediction of delaying
the branch update (0..n cycles), and impact between correct all vs only
miss branch corrections.
- (taken)Compare with SESC recent load/store queue papers (baseline,
SFB,
"A Power-Efficient and Scalable Load-Store Queue Design", and another
paper that I'll provide).
- (taken)Implement a LD/ST buffer on Verilog. I'll provide a paper explaining
the LD/ST queue model, and the interface. This project requires previous
experience with Verilog.
- (taken)SPECint 1000 ILP (Instruction Level Parallelism). Assume ideal
structures in the processor (perfect branch predictor, perfect
memory...). Measure the ILP, and propose new optimizations (cascading
units, value prediction, new compiler optimizations?) so that the ILP is
highly improved.
- (taken)Branch Prediction
Championship. Implement the SESC branch predictors, and compare the
results with other predictors like O-GEHL.
- (taken)Implement a division algorithm
on Verilog. If the division is fast enough on FPGA (over 130MHz @ Stratix
II) and ASIC (over 400MHz @ 180nm), the algorithm will be use on the
SCOORE project.
- (new)Create/extend the SPARC BIOS/PROM so that the serial port (UART) can
be used to download new kernel images.
- (taken)Use qsilver a GPU performance model with several computer games. The
evaluation should include performance/energy and temperature for a
couple of different GPUs. download.
- (taken)Boot opensolaris on the Leon3
processor (gaisler). Leon3 is a
stable platform capable to boot Linux. I'll provide FPGA boards and tools
to do the project.
- Implement the caches for SCOORE in Verilog. This project requires
previous experience with Verilog.
- Design a new architecture on gcc-sesc. Compare results with and
without optimization on wide superscalar processors usign SESC.
- (taken)Setup Linux infrastructure to run on FPGA boards running
Leon3. I'll provide the board, and the base infrastructure.
- Boot uClinux on an old SPARC 5 (SPARC V8) machine.
- (new)Upgrade SESC power models from power/wattch to power/panalyzer.
- (taken)We have a TLS (Thread Level Speculation) compiler on top of gcc 3.4.
The project is to upgrade the compiler to gcc 4.1.
- (new)Implement DIDUDE with the pin tools or gcc so
that it can work with c, c++.
- (new)Port SESC to 64bits. Currently, it compiles on 64bit
machines when -m32 flag is active. This is a long patch because long becomes
64bits instead of 32bits.
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