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Class Schedule
| Week of |
Tuesday | Thursday | Friday (lab) |
Slides |
Due |
| 01/02 |
| Introduction | none |
01intro |
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| 01/09 |
Review/Verilog I | Verilog II/Synplicity | setup/synplicity |
02verilog; 03verilog |
|
| 01/16 |
Explain projects | Verilog III & hw1-sol | none |
05verilog |
hw1 (01/17) |
| 01/23 |
Verilog IV | Testbenches | vsim |
06verilog ; 07testbench |
Project description (01/26) |
| 01/30 |
Coding Styles | Q&A | hw2 |
08coding ; verilogCoding |
hw2 (02/06) |
| 02/06 |
PSL/Assertions | FSMs & hw2-sol | Projects/hw3 |
09PSL ; 10fsm |
Project Interface (02/10) |
| 02/13 |
Q/A and examples | Skew Tolerant Circuit Design | Projects/hw4 |
11qa ; 12clock |
hw3 (02/17) |
| 02/20 |
ASIC vs Full-Custom & hw3-sol | FPGAs & ASIC | Projects |
dac2003 ; 14misc |
|
| 02/27 |
TCL & hw4-sol | Synthesis (dc/quartus) | Projects/hw5 |
15tcl |
hw4 (02/27) |
| 03/06 |
System Verilog | Coverage & hw5-sol | Projects |
16sv, 16sv1 ; 17misc |
hw5 (03/07) |
| 03/13 |
Projects Presentations | none |
18cov |
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| 03/20 |
no classes | none |
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Project due (03/23) |
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