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Homeworks (individually)
Homeworks should given before 06:00PM of the assigned day. Drop a
printed version at my office. If I am not there, place it under
the door.
Remember not to use tabspots and DOS special characters. To use the correct
format use the dos2unix.pl script frequently. It
removes tabs and \m characters.
Projects (individually)
Projects should be done either individualy. Complex project can be done by a
group of two (talk to me about it).
Projects have four major parts:
- Project description: A one page document explaining the main objective of the
paper. It should included a clear roadmap. The roadmap includes tasks and who does them.
- Project Interface: Commit the verilog module interface on the
class shared repossitory. The interface should compile but the modules can
be empty (just interface).
- Project presentation: 3-4 minutes powerpoint/keynote/latex presentation per each
project (around 5 slides).
- RTL Design and Verification: The source code commited to the
class repository would be analyzed, 20% of the grade would be based on the
Verilog design, 15% of the grade would be based on the verification of the
system (PSL included).
- Project Report: A 4-6 pages two column 11pt font size single
space. LaTeX should have a baselinestretch of 1 and article format. The
document should have an introduction, related work, experimental setup,
evaluation, and conclusions. Results to include on the report.
- Synplicity results: frequency, FPGA utilization, and technology
view for the critical path, and critical path explanation.
- Synopsys results for 200MHz, 400MHz, and 800MHz: area, power,
frequency, and critical path explanation.
- Testbench infrastructure, testing results, bugs found.
All the projects require a substantial amount of effort. Some projects can
easily be extended to become a master thesis or undergraduate project that I
can advise.
List of possible projects (cmpe202 required, may continue on this project on cmpe221):
- (taken)SCOORE FE/ID stages. Finish to implement/validate them
- SCOORE execution engine. Finish to implement/validate the cunit
- (taken)SCOORE Memory subsystem. L0s and L1.
- (taken)SCOORE FP Unit project (fadd, fmult) (use meiko FPU as a reference)
- (taken)SCOORE RAT (Rename Table) and ROB (Reorder Buffer) similar to Pentium IV (fronted RAT & retirement RAT)
List of possible projects (no cmpe202 required):
- (taken)Implement a noise radar. Use the Stratix II EP2S180 board.
- (taken)Make IVM (alpha EV67) synthesisable (try to follow MASC Coding Guidelines)
- (taken)Implement a torus, a fat-Tree, and some simple network for mnet (MASC
hypertransport-like network)
- Implement a wishbone/mnet bridge. Try 3 opencores wishbone systems
with the mnet network (assume fully connected but add random delays).
- Implement a distributed L2 cache for mnet (assume from 4 to 64 L2
cache nodes). Implement all the mnet commands.
- (taken)Implement SPARC VIS funtional unit (multimedia functional unit similar to altivec or MMX)
- (taken)Implement a Floating Point SQRT operation (SPARC V8)
- (taken)Implement the SPARC IOMMU with
DVMA (Direct Virtual Memory Access)
- Implement an thermal model on verilog (hot spot main loop
compute_temp)
- (taken)Implement a dummy terminal: VGA & PS2 keyboard. The characters typed
should be seen on the screen. Reuse the opecores ps2 and vga_lcd.
- (taken)Build a calculator on the FPGA board (+,-,/,*), access it through the
USB (opencores).
- Port leon or OR1K SDRAM controller to synos. Improve B/W and latency
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