CMPE 126: Advanced Logic Design

Information

• Lecture times: TTh 12-1:45pm, Social Science 2 165
• Lab: W 11-2, BE 115
• Instructor:
  
  • Matthew Guthaus (mrg@soe.ucsc.edu)
  • Phone: 459-4449
  • Office: E2-225
  • Office Hours: Tuesday 2-4 or by appointment
• TA: Keven Woo (klwoo@ucsc.edu)

Supplemental Information

• Verilog tutorial
• Verilog standard (only available on-campus)

Useful Things

• Icarus Verilog - Free Verilog simulator
• Emacs Verilog Mode
• GTKWave

Interesting Things

• Silicon Art Gallery