Two problems:
Below is a pla file (fa.pla) describing a Full Adder which will be used to illustate the process.
.i 3 .o 2 .ilb a b cin .ob s cout .p 8 000 00 001 10 010 10 100 10 011 01 101 01 11- 01 111 10 .eThe first two lines specify the number of inputs and outputs of your logic. The next two lines give the names of the inputs and outputs. The fifth line gives the number of product terms for which you will be providing the output values. Note that this might be less than 2n for n inputs because of don't cares in the inputs or outputs. The following lines consist product terms of the inputs for which you provide the values for the outputs. For example, 011 01 means that (~a)b(cin) is a term in the sum of products for cout, but not for s. Thus cout will be 1 when a=0, b=1, and cin=1 while s will be 0 (unless there is some other product term that covers this case where s=1). Take for example, the last two product terms. the line 11- 01 will make cout=1 when a=1 and b=1.
Step 1: Use espresso to map don't cares and
perform two-level minimization on the pla file
z4ml.pla.
Here's how you would do it for fa.pla.
espresso -Dmapdc fa.pla | espresso > faOPT.pla
Step 2: Use the SIS program to perform multi-level logic minimization on the new pla file you created in Step 1. Below is a session using faOPT.pla. Try to get the smallest number of literals. You may want to try script.boo as well.
>C:sis
UC Berkeley, SIS 1.3 (compiled May 28 1995)
sis> read_pla faOPT.pla
sis> p
{s} = a b cin + a b' cin' + a' b cin' + a' b' cin
{cout} = a b + a cin + b cin
sis> ps
faOPT.pla pi= 3 po= 2 nodes= 2 latches= 0
lits(sop)= 18 lits(fac)= 15
sis> source script
sis> ps
faOPT.pla pi= 3 po= 2 nodes= 2 latches= 0
lits(sop)= 15 lits(fac)= 12
sis> p
{s} = {cout}' a + {cout}' b + {cout}' cin + a b cin
{cout} = a b + a cin + b cin
sis> clp
sis> source script.alg
sis> ps
faOPT.pla pi= 3 po= 2 nodes= 4 latches= 0
lits(sop)= 14 lits(fac)= 14
sis> p
{s} = [5] a + [5]' a'
{cout} = [6] a + b cin
[5] = b cin + b' cin'
[6] = b + cin
sis> write_eqn fa.eqn
sis> quit
Step 3: Print out and turn in the eqn file. Report the number of literals (as determined by sis).
Step 4: Import this combinational circuit into foundation as an XNF macro by translating the eqn format to XNF and adding input/output pads and buffers to the schematic.
.i 3 .o 3 .s 4 # highway traffic light controller # inputs: C Tl Ts # car sensor, long timer, short timer # outputs: St H F # Start timer, HF=00 Highway Green # 01 Highway Yellow # 10 Farm Green # 11 Farm Yellow #.ilb C Tl Ts #.ob St H F 0-- S0 S0 000 # keep Highway green if no car -0- S0 S0 000 # or if time Tl has not expired 11- S0 S1 100 # else goto Highway yellow and start timer --0 S1 S1 001 --1 S1 S2 101 10- S2 S2 010 0-- S2 S3 110 -1- S2 S3 110 --0 S3 S3 011 --1 S3 S0 111
The first three lines describe the number of input bits (3 bits), the number of output bits (3 bits), and the number of state bits to use (not the number of states). The remaining lines describe the state transitions and the associated inputs (x), outputs (z), for present state (PS), and the next state (NS).
Use mustang to assign states to state machine in the STT file and generate the combinational login as a pla (programmable logic array) file
mustang -l file.fsm > file.pla
Here file.pla is the combinational circuit for the finite-state
machine in pla format as follows:
.i 7 .o 7 .ilb x2 x1 x0 PS3 PS2 PS1 PS0 .ob NS3 NS2 NS1 NS0 z2 z1 z0 0-- 1--- 1000 000 -0- 1--- 1000 000 11- 1--- 0100 100 --0 -1-- 0100 001 --1 -1-- 0010 101 10- --1- 0010 010 0-- --1- 0001 110 -1- --1- 0001 110 --0 ---1 0001 011 --1 ---1 1000 111
The argument to mustang tells it which state assignment scheme to use:
usage: mustang [options] input_file
General Options:
-d: debug
Encoding Options:
-ran: dynamic random encoding
-r: deterministic random encoding
-s: sequential encoding
-l: one hot encode FSM
Multi-level State Assignment Options:
-n: fanin oriented algorithm
-p: fanout oriented algorithm
-t: favor two-level implementations
-c: wedge clustering algorithm for embedding
-a: annealing algorithm for embedding
-e: expand state codes
-i: specify annealing parameters
-x: approximate by discarding edges in graph
-o: generate one hot like codes
-onehot: onehot relationships from blif file
For one-hot encoding use the -l option (not -onehot).
Options t, c, a, e, i, x, o, onehot are not working at the moment.
Your task: Translate the state machine from the Digital Stop Watch/Timer example in STT format. Use mustang to encode your state machine with two different encoding schemes.
For each of the two schemes (pla files) follow Steps 1 through 4 of Problem 1. Report which scheme gives the best result.