Homework 2

Due: Friday April 9 by 2:00pm.

Problems:

  1. Construct a 3-bit counter with inputs and outputs as pictured below.

    The Terminal Count(TC) is high when the 3-bit count (Q2 Q1 Q0) is (1 1 1). Realize your counter with a XC4003EPC84 Xilinx FPGA on the demo board. Use pin 13 of the XC4003E as your clock input. To do this you need to:
    1. Edit block P13 to make sure the pad is connected to the CLKIN pin of this block.
    2. Add a net between the CLKIN pin of P13 and the input pin of the global buffer (BUFGP_TL.I) See the figure below for location of these terminals.

    3. Add a net (say CLK) to BUFGP_TL.O and all of the K terminals of the CLBS in which you need the clock (those in which you use the flip-flop).
    The four outputs of the counter should be displayed on the 4 general purpose LEDS (CR2 on the demo board). These are already connected to pins 61, 62, 65 and 66 of the XC4003E-PC84. To turn on the LED you will need to drive the pin low, so you'll probably want to invert the output of your counter; this can be done in the IOBs.

    The input, UP, will be from the spare pushbutton. The counter should abvance by one every time you press this pushbutton. One side of the pushbutton (J5) is connected to ground and the other side is connected to pin 47 of the XC4003E-PC84. With the pullup on in IOB of P47, depressing the spare pushbutton gives a low going pulse. You will need to debounce this pulse and detect a high to low edge in order for your design to work properly. (Use a counter to sample the input more slowly to remove noise and the edge detector from Homework 1 to get only a single pulse.)

    Follow these steps:

    1. Work out your design and how you plan to implement it with CLBs on paper. The fewer CLBS, the better and easier.
    2. Use fpga_editor to enter your design and create an ncd file.
    3. Use bitgen to create a bit file from your ncd file: bitgen counter3.ncd
    4. Use hwdebugr to download your bit file. Either provide the bitfile as an argument to hwdebugr at the prompt or type open counter3.bit in the console window to read in the bitstream.

    You must show me your working circuit by the due date.

    You should draw and submit:

    1. The logic diagram of your design.
    2. A diagram to illustrate the mapping between the logic circuit and CLBs as well as their interconnection in the XC4003E FPGA.
    3. Print out a map of the XC4003E LCA (logic cell array) and indicate on the map the placement of the used CLBs and the IOBs.

  2. This exercise is designed to familiarize yourself with the Tektronics digital oscilloscopes in the lab. Please do not disconnect the cap and clip from the probes.

    You are given two related design files: cnta.bit and cntb.bit. They are both 4-bit binary counters. For each counter, the terminal count TC is connected to the I/O pin P9. I've deposited these files in the directory C:\hw2 of the PCs that have demo baords.

    Using the design file cnta.bit, please follow the given steps.

    1. Write down and report the bench number of the PC you are using.
    2. Power OFF the demo board and the oscilloscope.
    3. Use two probes of the oscilloscope, connect one of the probes to P9 (orange jumper wire) and the other probe to jumper wire on P13 of the demo board.
    4. Power ON the demo board, and the oscilloscope.
    5. Configure the demo board using the design file cnta.bit.
    6. Use the oscilloscope to display the CLOCK and TC, as shown in the figure below. (Recall that the clock on the demo board is 20Mhz.)

      Counter cnta output.

    7. Count of number of clock pulses in between the TC cycle and report this number (and the number of the PC you are using).

    Repeat the steps above using instead the design file cntb.bit.

    1. Again count and report the number of clock pulses in between the TC cycle.
    2. Locate the glitch in TC relative to the CLOCK. Count and report the number of clock pulses between the preceding TC pulse and the glitch.
    3. Measure and report the width and voltage level of the glitch using the measurement menu of the oscilloscope.
    4. Use the cursors to measure and report the width and height of the glitch.
    5. Power OFF the demo board, the oscilloscope, and the signal generator. Thank you.


    Counter cntb output.

    3. The CMPE126 Web:
    Copyright 2004; Department of Computer Engineering, University of California, Santa Cruz.
    martine@cse.ucsc.edu