Due: Monday April 5 at the beginning of class.

Problems:

1. An falling edge-detector is a machine with a single input whose output goes low for exactly one clock cycle when the input goes low and stays low until the next clock. We assume that the input changes at a slow enough rate that it does not have two transitions within any single clock period. (If it does the detector may miss them.)

   
   

   Provide the following:

   1. A state diagram of the Finite State Machine (FSM) of your edge detector.
   2. The encodings used to represent the states.
   3. The Karnaugh maps describing the logic equations of your design.
   4. A logic diagram of the implementation of the FSM.
2. A sequential comparator takes two bit streams representing two binary numbers least significant bit first and indicates either that
   1. the number represented by the first stream is larger,
   2. equal to, or
   3. less than,
   the number represented by the second stream. The figure below shows the inputs and outputs of the sequential comparator. The bits of the two streams are synchronized with the clock input.

   
   

   The output signal G should be asserted when the stream received so far on the X input is greater than the stream received on the Y input. The output signal E should be asserted when the two bit streams are the same so far which includes the case in which no bits have been presented. To initialize the comparator before presenting new bit streams, your flip-flops will be reset to 0 using existing built-in circuitry. Hence when your flip-flops are 0 you should be asserting E.

   Provide the following:

   1. A state diagram of the Finite State Machine (FSM) of your comparator.
   2. The encodings used to represent the states.
   3. The Karnaugh maps describing the logic equations of your design.
   4. A logic diagram of the implementation of the FSM.
3. A vending machine sells candy for 30 cents. It accepts nickels, dimes and quarters and provides no change if more than 30 cents is deposited. Design a finite state machine to control the vending machine. The inputs to the machine are two signals indicating which coin has been deposited or that a coin release is requested. The 4 possible inputs are encoded by the two signals as:

   
   00 nickel deposited
   01 dime deposited
   10 quarter deposited
   11 coin release

   
   

   Assume that your machine will receive a clock only when there is an input (a coin has been deposited or the coin release has been pulled). These two signals are synchonized with a clock. The outputs of your machine are two signals: one releasing the candy and the other releasing the coins.

   Provide the following:

   1. A state diagram of the Finite State Machine (FSM) of your vending machine control.
   2. The encodings used to represent the states.
   3. The Karnaugh maps describing the logic equations of your design.
   4. A logic diagram of the implementation of the FSM.

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Copyright 2004; Department of Computer Engineering, University of California, Santa Cruz.
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