As in your midterm, the PC writes and reads 8-bit words from output ports at addresses 0x0304 and 0x0305. The location of a move is encoded as:
D7 D6 D5 D4 D3 D2 D1 D0
Move encoding = WR PA R2 R1 R0 C2 C1 C0
R2 R1 R0 is the row index starting from 0 at the top and
C2 C1 C0 is the column index starting from 0 at the left.
There is a one-bit WR flag (the most-significant bit) at address 0x0304 that indicates when White's move is ready. This signal is active low. The seventh bit, D6, is 1 when the move is a PASS. Otherwise, the location of the move is presented as the 6 other bits of the byte written to to port 0x0304. As an example, if White moves to d6 (row 6-->101 and column d-->011), then the PC will write the following two bytes to port 0x0304.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 0 1 0 1 1
1 0 1 0 1 0 1 1
The resulting positive edge detected on D7 indicates that the
other 7 bits represent White's move. If White passed, then the following
two bytes would be written
D7 D6 D5 D4 D3 D2 D1 D0
0 1 ? ? ? ? ? ?
1 1 ? ? ? ? ? ?
Your Othello machine reads the outport port 0x0304 and saves the location of White's move in a bank of 7 registers.
After figuring out where Black should move, your Othello machine should assert (low) BR on bit D7 of port 0x0305 while presenting Black's move on the other 7 bits. Note that since you don't know exactly when the PC will read this port, you must have Black's move on bits D6 through D0 before asserting BR. You must continue to hold it there and keep BR asserted until you receive White's next move (i.e. until WR is asserted). Then you must promptly deassert BR so that the PC will not read this move again.
The host (program) will assert the global reset signal (P10) that resets all the flip-flops before each game. Note that the initial contents of any RAMs on the FPGAs will not be reset by this signal. You will need to restore them to the proper state to restart the game.
The port assignments in the R1 FPGA are:
I/O Address: 0x300 Function: used by X0
I/O Address: 0x301 Function: used by X0
I/O Address: 0x302 Function: used by X0
I/O Address: 0x303 Function: Global Reset- used by X0
I/O Address: 0x304 WhitePORT (from PC to Othello machine)
Bit 7 6 5 4 3 2 1 0
---------------------------
| WR PA R2 R1 R0 C2 C1 C0 | WR = 1 White not ready
| loc White's move | WR = 0 White move ready
--------------------------- PA = 1 White passes
PA = 0 White move is R2 R1 R0 C2 C1 C0
I/O Address: 0x305 BlackPORT (from Othello Machine to PC)
Bit 7 6 5 4 3 2 1 0
---------------------------
| BR PA R2 R1 R0 C2 C1 C0 | BR = 1 Black not ready
| loc White's move | BR = 0 Black move ready
--------------------------- PA = 1 Black passes
PA = 0 Black move is R2 R1 R0 C2 C1 C0
I/O Address: 0x306 not used in this project
I/O Address: 0x307 not used in this project