CMPE 126 - Advanced Logic Design - Fall 2006
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Class Schedule

Week of Tuesday Thursday Lab Slides Due/Misc
09/18 Introduction none 01intro
09/25 High-Level Design Structured Design Synos Setup 02struct ; 03struct matrix01
10/02 Infrastructure/Flow Verilog I none 04flow ; 05verilog hw1 (10/03)
10/09 Verilog II Testbench Synthesis Tools 06verilog ; 07testbench hw2 (10/10)
10/16 Testbench II Testbench II no-lab 07vpi
10/23 Verilog III ASIC/FPGA Go over hw3 08verilog ; 09fpga hw3 (10/24)
10/30 Midterm Coding Style hw4 10coding hw4 (11/03)
11/06 PSL/Assertions FSMs 11psl ; 12fsm
11/13 Power Skew Tolerant Circuits 13power ; 14clock hw5 (11/16)
11/20 Coverage Holiday 15cover
11/27 System Verilog & Q/A Projects & Review none 16sva, 16sv hw6 (11/28) ; Project (11/30)
12/04 no classes none Final Exam