CMPE 125: Logic Design with Verilog

Information

• Lecture times: MW 5-6:45pm, BE 165
• Lab: T 6-7 (reserved until 8), BE 115
• Instructor:
  
  • Matthew Guthaus (mrg@ usual ucsc suffix)
  • Phone: 459-4449
  • Office: E2-225
  • Office Hours: Tuesday 1-2, Wednesday 4-5
• TA: Andrew Hill (awhill@ usual ucsc suffix)

Supplemental Information

• Verilog tutorial
• Verilog standard (only available on-campus)

Useful Things

• Icarus Verilog - Free Verilog simulator
• Emacs Verilog Mode
• GTKWave

Interesting Things

• Silicon Art Gallery