CMPE 125/L: Logic Design with Verilog

Information

• Lecture times: TTh 4-5:45pm, Physical Sciences 140
• Lab: Tuesday 12-2, Thursday 6-8, BE 115
• Instructor:
  
  • Matthew Guthaus (mrg@soe.ucsc.edu)
  • Phone: 459-4449
  • Office: E2-225
  • Office Hours: Tuesday/Thursday 2-3:30 or by appointment
• Teaching Assistant:
  
  • Walter "Jas" Condley (jas@soe.ucsc.edu)
  • Lab: BE 115
  • Office Hours: Wednesday 12-2 (and in lab)
• Course Forum

Supplemental Information

• Xilinx ISE 12.2 Tutorials
• Xilinx ISE 10.1 Quick Start Tutorial (slightly out of date, but much shorter!)
• Verilog tutorial
• Verilog standard (only available on-campus)
• C. Cummings, "full_case parallel_case", the Evil Twins of Verilog Synthesis, SNUG 1999.
• C. Cummings, Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!, SNUG 2000.
• Sutherland HDL

Useful Things

• Icarus Verilog - Free Verilog simulator
• Emacs Verilog Mode
• GTKWave - waveform viewer
• Audacity - audio editor/viewer
• Pure Data - real-time audio environment

Interesting Things

• Silicon Art Gallery