...A Single Cycle chip's clock period is set to the time it takes to
executing the longest instruction...

...A MultiCycle chip's clock period is set to the time it takes to execute a
microinstruction...

Therefore the MultiCycle chip is at a lower level of abstration than the
Single Cycle...MultiCycle is in relation to the different stages of an
instruction computation...Single Cycle, in relation to the instruction as a
whole.

The PipeLine chip you are learning about is like the MultiCycle in terms of
having different stages of an instruction execution...
In Pipeline, unlike MultiCycle, you are executing multiple microinstructions
in parallel...This is the utter importance of the save registers at the end
of each pipeline stage.  You must not only propagate the instruction and its
computations between the different stages, you must also pass its control
signals and PC (because of branch and jump)....

So when you think about pipeline, think about what the contents of the
"save" registers are at the end of each stage...And REALIZE that a "save"
register is read at the beggining of a cycle and written to the next (right)
"save" register at the end of the cycle.....This is how data and control is
preserved along the pipeline....This is important.

Also, think about datahazards (control and data).....What happens when you
have to execute a branch's zero signal?  Should you pipeline in the next
instruction or the branch address instrction?!....What about reading a
register that hasn't been written to yet.....What happens if you need the
ALU and something else wants it (why we compute branch for non branch
instructions?!!?) ?  This is comming up....Think about it though...its also
in the book...the book is cool...

Marko.

--
http://www.nenofhat.net/okram
http://people.ucsc.edu/~okram