CmpE 110 HW 6

Date Due: Monday, Nov. 17, 2003 Beginning of Class

Timing Analysis of the 3 Data Paths

Figure 1: Single Cycle Implementation from slide 8-18

Figure 2: Multi-Cycle Implementation from slide 9-7

Figure 3: Pipeline Implementation from slide 10-8

Memory Reads or Writes take 3ns.  Register File Reads or Writes take 2ns.   Register (data or pipeline) Writes take 1ns.  The ALU takes 4ns to propagate a result.  Multiplexors and simple adders take 1ns to propagate an input.  Shifting and sign extending is negligible time. 

Code Segment 1:   

BeginLoop: lw $1, 100($10);

        lw $2, 108($10);

        addi $11, $2, 50;

        lw $3, 104($10);

        addi $12, $3, 55;

        addi $13, $1, 60;

        sub $14, $11, $3;

        add $15, $12, $1;

        add $16, $13, $2;

        slti $17, $2, 275;

        addi $18, $0, 1;

        sw $14, 100($10);

        sw $15, 104($10);

        sw $16, 108($10);

        beq $17, $18, BeginLoop;

Assume initially that Mem[100 + $10] = 25, Mem[104 + $10] = 45, Mem[108 + $10] = 10;

Course-relevant instruction set : add, sub, and, or, addi, andi, ori, beq, j, lw, sw, slt, slti

Questions

1.) For Single Cycle implementation, calculate the clock period length, and its corresponding maximum frequency using the given timing parameters listed above for all course-relevant instructions. (1/2 point each)

2.) For Multi-Cycle implementation, calculate the clock period length, and its corresponding maximum frequency using the given timing parameters listed above for all course-relevant instructions.  Also compute the CPI for each course-relevant instruction using this implementation. (3 points)

3.) For the Pipeline implementation, calculate the clock period length and its corresponding maximum frequency so that each pipeline stage may finish its work.  Please note that a pipeline implementation cycle ends by writing data to the pipeline register. (1/2 point each)

4.) Using Code Segment 1 and answers from above, determine the execution time of the program for each implementation.  The pipeline is finished when no more instructions remain within the pipeline.   *note for the pipeline implementation you may use forwarding to avoid wasted clock cycles    (3 points)

5.) Using the Pipeline implementation and Code Segment 1.  What is the value of EX/MEM.ALUresult pipeline register during the 8th clock cycle?  (1 point)

6.) Using the Pipeline implementation and Code Segment 1.  What is the value of ID/EX.Read1out pipeline register during the 10th clock cycle?          (1 point)