CmpE 110

Homework #5   ISA + Single Cycle Datapath

Due : Monday November 3, 2003

You have the honor of designing the instruction set architecture and datapath for the new DiBlas SCPOS processor.  Your design should follow the parameters set below.

• Register - Register RISC Architecture
• Single Cycle
• 3 byte instruction word
• Instructions to be used: Add, AddI, Sub, SubI, LW, SW, J, JR, BEQ, BNQ, AND, ANDI, OR, ORI, NOP, SLT
• Separate Instruction memory and Data Memory each is byte addressable and is 64K in size.  Reads and Writes take 3ns each.
• 16 16-bit registers.  Reads and Writes take 2 ns each.
• 16-bit ALU that will do addition, subtraction, AND, OR.  2 ns propagation delay
• Multiplexers, Logic Gates, Sign Extenders, Adders, 3x multiplier, and Shifters are at your disposal, each with a 1ns propagation delay. 

1.) Design the instruction layout for each of our MIPS instruction formats (R, I, J). (2 points)

2.) Define your Immediate Range (for Branch and Immediate ALU instructions) and your Jump Range (Jump only instruction for J type). (1/2 point each)

3.) Draw out your datapath, similar to slide 8-18, titled All Together.  Define each signal vector going between units (like in the slide).  Label each unit appropriately.  Create a control unit (defined as an oval) and draw each of the needed inputs and outputs to control your datapath units, including the ALU.  (4 points)

*Notes: Be careful in implementing Branch and Jump parts of the datapath.  The value in the immediate and jump fields identifies how many instructions to branch/jump to from the Next PC. 

4.) How short can we make the clock cycle?  Draw a table out showing how many clock cycles are used on each type of unit, for each instruction  (ie a table where each row is an instruction, and each column is a functional unit, and the last column is the total column.)  (3 points)