CmpE 110

HomeWork Set 2

Due October 13, 2003

A person wishes to have a X input, 1 output electronic unit that will calculate 4 input bits on 5 different functions.  A multiplexor will be used to determine which functions output will be sent as output of the unit.  (the design should basically calculate all 5 functions in parallel, and have the multiplexor select the appropriate function) 

Below are the 5 functions: (+ = OR, ' = not, and inputs directly next to each other are ANDed together)

F = ABC + A(CD + B') + CD'(A + B)'

G = A'B + CB'(A+D) + CB(AD' + CD)

H = A'B'CD + A'B'(C' + D') + (ABC)'

I = D'(A + B') + CD(A' + B)'

J = A'(B+D') + A'B'C'D + AB(C' + D)'

Propagation delay of gates to be used: OR = 5ns, AND = 4 ns, NOT = 1 ns

1.) Determine how many control bits is needed to operate the multiplexor?  Then give the total of inputs needed (X). (1 point)  Control Bits = CEILING( log₂ Mux inputs) = 3; Total Inputs = 4 (inputs bits) + 3 (mux control bits) = 7

2.) Draw out each of the 5 functions w/o simplification. Calculate the worst case path for each function, and what ABCD input(s) are needed to cause this worst case path.  (Note that gates do not have to wait for all inputs to change its output.  eg if a 0 is sent to an AND gate, its output is automatically 0, and if a 1 is sent to an OR gate its output is automatically a 1)  Show all work. (15 points)  Page 1 of Answers       Page 2 of Answers   

3.) This person wishes to accomplish as much work as possible, so a memory element is used (such as a register or ROM) to have the next set of inputs ready every time the selected function finishes its work and has sent its output to the user (via some mechanism we are not concerned with).  Assuming a multiplexor propagation delay of 5ns, how short can we make our clock cycle?  Answer in terms of clock period and frequency.  This clock cycle should be long enough to handle all cases of inputs so that the true output is always displayed at the end of the clock cycle. (4 points)

From Problem 2, the function with the longest Worst Case Path is Function is G, which is 19ns.  So the shortest we can make the clock cycle is Tcc = 19 ns (longest WCP) + 5ns (MUX) = 24 ns.   F = 1 / T = 1 / 24e-9 = 41.66 MHz

4.) Now take these functions and simplify them using a Karnough Map so that they may be put in canonical form (minterms or Sum of Products).  Write out the new equations, and show your work.  (5 points)

 Page 1 of Answers  Page 2 of Answers

5.) What is the clock period and frequency of the simplified function implementation? (1 point)

Since canonical form is a 2 level implementation,  the NOT inputs are calculated in parallel, then a level of AND gates then a final OR gate.  So total clock period time is 1 ns (NOT) + 4 ns (AND) + 5ns (OR) + 5ns (MUX)= 15 ns = clock period

Frequency = 1 / Clock Period = 66.6667 MHz