CMPE 12 Links Main page Course information Class notes Filled-out notes Homework Labs Lab Write-Ups SOE Forums Off-site Links Textbook Lab Manual BELS IEEE Chapter SWE Chapter Other links Intro to Extreme Programming Paired Programming research paper CPU Information Center Cool die photos Number representation analysis in C White Paper on Caches by Intel The ASCII Table! Ghostview (postscript viewer) Typing injury FAQ (TIFAQ)		Recent Forum Posts Today is Monday, May 21, 2012 view forum Nothing available at this time.
	Lab 1: Introduction to Logic Design Due date Due into the locker by Monday, June 29, at 8:00am Lab Objective Welcome to CE12L! This is the first lab of three that uses the Multimedia Logic (MML) application by Softronix in Windows. MML is a free schematic entry and simulation tool, so you can download it and install it at home as well, if you wish. You will use MML to build some simple circuits, developing your circuit-building intuition! Note: Do not visit the Softronix Website as it is labeled as an unsafe page. It may be infected with malware and may harm your computer. Use the link provided above instead. You are expected to finish part A of this lab during the first lab section day, and parts B and C during the second lab section. This lab assignment is worth 32 points. Of these, 20 points are on the lab itself, and 12 points are on the lab report which you will submit. Lab tutors: Go over these topics Your lab tutor will cover the following topics in the first 40 minutes of lab. Introductions When labs are due What's required when submitting a lab: submitting the lab files and a detailed lab report (More...) To submit your work, you need a UNIX account on the UCSC server. If you do not have one, talk to your tutor. Transfer your files to the UCSC server. If you are in the BE109 or other IT lab, you can just drag and drop your files into your home directory (labeled X:). Otherwise, you will need to FTP your files over. Use SFTP or a similar secure FTP program to transfer files. Open a connection to unix.ic.ucsc.edu with your username and password, and place the desired files into the desired directory on the UCSC server. Connect to the UCSC server via SSH. Open a connection to unix.ic.ucsc.edu with your username and password. Go into the directory which has your files. Use cd directoryname to change directories. Type the submit command: submit cmpe012l-fire.u09 labn-tutorname files..., where n is the number of the lab (this is lab1) and tutorname is the first name (all lowercase) of your tutor. How to use sum of products to go from a 3-input, 1-output truth table to logic gates Warm-up: Multimedia Logic Multimedia Logic (MML) allows you to build logic gates and connect them together. In the warm-up, you will read the tutorial and get familiar with the basic logic elements on the palette. What's required You must submit lab1_warmup.lgi into the lab locker. A report is not required for this portion of the lab; we are learning the commands to submit into the lab locker. Procedure: Tutorial Start the Multimedia Logic (MML) tool. You can find it in F:\Class Folders\Computer Engineering\CE 12L\Mulimedia Logic. The executable is called Mmlogic.exe. Run the tutorial. Go to Help>Tutorial. This tutorial will walk you through building and simulating a simple circuit. Use the text tool to put your name, lab section, date, and lab number on your schematic. Save the resulting schematic as lab1_warmup.lgi. If you are in BE109 or other IT lab, save the schematic in X:, your mounted drive on the UCSC file system. That way, you can access your project later. All files left on the lab computer are deleted as soon as you log out. If you are in another lab, remember to transfer your files to your home directory when you are done. Create a directory especially for CE12. Create another one especially for lab 1. Save your schematic in there. Procedure: De Morgan's Laws Now, experiment with the logic gates by showing De Morgan's Laws in action. Save the resulting schematic as lab1_demorgans.lgi and submit it when you are done. Connect two switches to an AND gate. Connect the output of the AND gate to an LED. See what happens on the output when you change the inputs. Figure 1 shows how to add a switch from the palette. Figure 1: Adding a switch from the palette Now, add an an inverter between the switch and the AND gate for each input. Refer to Figure 2. Figure 2: AND gate with inverted inputs Connect the same two inputs to an OR gate and corresponding LED. Change the OR gate to a NOR gate: Right-click on the OR gate, select Properties, and choose "Invert Output (NOR)." Refer to Figure 3. Figure 3: Inverting the outputs for a two-input OR gate to create a NOR gate Demonstrate De Morgan's Laws by running the circuit simulation and seeing that the two LEDs show the same output. Submit lab1_warmup.lgi and lab1_demorgans.lgi into the class locker. Connect to unix.ic with SSH Log in with your UCSC username and password cd into the directory with your lab 1 files Submit your files: the submit command for lab 1 is submit cmpe012l-fire.u09 lab1 filenames... Lab 1, Part A: Sequential logic Now we're ready to start! Implement the truth table shown in Figure 1. You may use and, or, and not (inverter) gates. What's required You must submit lab1_a.lgi and the associated lab report into the lab locker. You may submit just one lab report for the two-part lab assignment below. That is, your lab report may contain documentation relating to both parts (a) and (b). In particular, your design must Implement the truth table shown in Figure 1: It must have 3 inputs, such as switches, and one output, such as an LED, that lights up when the output is 1 and stays off when the output is 0. Use any sequential logic gates you like. Have, as a text element, your name, lab section, date, and lab number. In addition to the standard things a lab report has, your lab report must Explain how you went from a truth table to a logic design. State the number of transistors needed for your design. Figure 3 shows the numbers of transistors for our commonly-used logic elements. A B C OUT 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 Figure 1: Truth table to implement for part A Procedure Following these steps may help you get started. Work out the logic needed to obtain the TRUE (1) output OUT from the three inputs A,B,C on a piece of paper. Open a new file in MML, and save it as lab1_a.lgi. Add your name, lab section, date, and lab number to your design using the text tool. For the three inputs A,B,C add three switches. For the one output, OUT, add an LED. If you visit the properties of the LED, you can change its color! Add the logic you designed in step 1 to connect the switches to the LED. Test your design by trying each of the combinations of inputs and watching for the expected behavior (will the light turn on?). Document your steps in the lab report. Count the number of transistors your design took. Figure 3 shows the logic gate to transistor conversion. Document the number of transistors in your lab report. Show your lab to your tutor for a checkoff (optional). Submit your lab and report to the course locker. 2-input gate Transistors AND 6 OR 6 NOT 2 (1-input only) NAND 4 NOR 4 XOR +/-14 Figure 3: Number of transistors needed for each two-input gate. Additional inputs require 2 more transistors each, per gate. Lab 1, Part B: Optimization Optimize the circuit you designed in part (a) above for speed and user-friendliness. What's required Submit lab1_b.lgi and the associated lab report into the lab locker. You may submit just one lab report for the two-part lab assignment. That is, your lab report may contain documentation relating to both parts (a) and (b). In particular, your design must implement the truth table shown in Figure 1, but with the following changes. Minimize the propagation delay through the circuit. That is, optimize the circuit for speed. You can assume that the more transistors there are in a circuit, the slower the circuit will be. Use the numbers in Figure 3 to minimize the number of transistors in your design. Use a keypad for entry instead of switches. That is, optimize the circuit for user-friendliness. We hate switching all those fake switches. In addition to the standard things a lab report has, in your lab report, you must Talk about the changes you made to your design, and the improvement over the previous number of transistors in your design Mention DeMorgan's Laws and how -- or if -- you used them to modify the logic Answer this question: Why do AND and OR gates use more transistors than NAND and NOR? Figure 4: Keypad element Grading template Logic design requirements This is a suggested grading rubrik. Your tutor may or may not use this rubric to grade by, but it is a good general guideline before submitting your lab to check off these points. (1 pts) Complete the simple tutorial (8 pts) Part A: Implement the logic with sequential logic gates (6 pts) Part B: Optimize the circuit for number of transistors (4 pts) Part B: Add the keypad (1 pts) Have the schematics labeled (name, lab #, title, date, etc) 20 points total Lab write-up requirements In the lab write-up, we will be looking for the following things. The lab report is worth 12 points. We do not break down the point values; instead, we will assess the lab report as a whole while looking for the following content in the report. The typical things a lab report should have. Read more about lab reports before submitting yours. Discuss the original design. How did you get to the logic design from the truth table? How many transistors in the original design from part (a)? Discussion the changes you made to your design. How many transistors in the improved design from part (b)? Discussion of DeMorgan's Laws and how -- or if -- they were used them to modify the logic from part (a) to part (b). Why do AND and OR gates have more transistors than NAND and NOR? 12 points total
	This page maintained by fire

impact-silly